| IP명 | Time Interleaved Dual-Residue Pipelined SAR ADC with Fully On-Chip Digital Background Calibration | ||
|---|---|---|---|
| Category | Mixed | Application | RF Sampling Circuits |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1V |
| IP유형 | Hard IP | 동작속도 | 2GHz |
| 검증단계 | Silicon | 참여공정 | SS28-2501 |
| IP개요 | A 12b Time Interleaved Dual-Residue Pipelined SAR ADC utilizing a fully digital on-chip background timing skew calibration suitable for any number of channel. | ||
- 레이아웃 사진 -
|
|||