| IP명 | Recovery-Signal-Based Low-Cost Quadruple-Node-Upset-Tolerant Self-Recoverable Latch Design | ||
|---|---|---|---|
| Category | Digital | Application | Memory |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1V |
| IP유형 | Hard IP | 동작속도 | 100MHz |
| 검증단계 | Silicon | 참여공정 | SS28-2501 |
| IP개요 | Innovative low-cost latch designed with self-recovery characteristics to address node upsets using a dedicated recovery signal. | ||
- 레이아웃 사진 -
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