| IP명 | Wideband Inverter-based Low-Noise Amplifier and Variable Gain Amplifier in 28-nm FD SOI | ||
|---|---|---|---|
| Category | Analog | Application | wireless com. |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1V |
| IP유형 | Hard IP | 동작속도 | 20GHz |
| 검증단계 | Silicon | 참여공정 | SF028-2501 |
| IP개요 | – This proposal introduces a wideband inverter-based low noise amplifier (LNA) and variable gain amplifier (VGA) for multi-standard applications. By utilizing the inverter-based topology, both circuits achieve high gain while minimizing power consumption and area. Additionally, the enhanced low-frequency gain provided by this topology facilitates the realization of a wide 3- dB bandwidth. For the LNA, shunt-series transformer feedback technique is proposed to simultaneously achieve wideband input matching and low, flat noise characteristics. Interstage noise and conjugate matching at high frequencies are realized through a series inductor (L1) and source degeneration inductor (Ls) in the second stage. Additionally, two peaking inductors (Lg, L3) and inductive load (L4) extended the 3-dB bandwidth. In the VGA, a PMOS varistor is employed as the second-stage load to broaden the gain control range (GCR) while maintaining flat gain response. Both circuits are implemented in a 28-nm FD-SOI CMOS technology. The LNA exhibits a simulated 3-dB bandwidth of 4.7-32.8 GHz with a S21,peak of 22.7 dB. The input matching remains below -10 dB 4.6- 37.1 GHz, and the NF ranges from 2.5-3.25 dB within 3-dB bandwidth. The LNA consumes 9.9 mW of DC power and occupies a core area of 400 × 242 ????????2 . The VGA achieves a simulated 3- dB bandwidth of 5.1-34.5 GHz and a S21,peak of 18.9 dB in maximum gain mode, with GCR of 17.2 dB. The NF varies between 4.32-5.43 dB, and the VGA consumes 41.3 mW of DC power with a core area of 661 × 343 ????????2 . |
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