| IP개요 |
This prototype introduces a pipelined successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes interleaved residual amplifiers. Although floating inverter-based (FIA) amplifier shows the advantages of that high energy efficiency, easy maintenance of the output common mode voltage (VCM), it is hard to utilize FIA amplifier as a residual amplifier in pipelined ADC due to slow operation of FIA. In order to utilize FIA in pipelined ADC, the time-interleave amplifier architecture is proposed in this paper. The proposed architecture of pipelined SAR ADC consists of two stage: the first stage of the ADC employs a hybrid Flash-SAR sub-ADC architecture, and the second stage of the ADC adopts a nonbinary ping-pong SAR structure, where two dynamic comparators operate alternately after the DAC settles. As a prototype ADC, an 11-bit 1-GS/s ADC is designed for demonstrating advantages of proposed architecture under 1-V supply and 2Vpp input range. This prototype demonstrates the potential for implementing a pipelined SAR converter that achieves high-speed operation, high accuracy, and excellent energy efficiency. |
