| IP명 | A 6.4GHz Double-Subsampling PLL with configurable BW and Achieving 50-fs-rms Jitter with SCR-based DCC | ||
|---|---|---|---|
| Category | Analog | Application | PLL |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1.2V |
| IP유형 | Soft IP | 동작속도 | 6.4GHz |
| 검증단계 | Silicon | 참여공정 | SS028-2502 |
| IP개요 | A 6.4GHz Double-Subsampling PLL with configurable BW and Achieving 50-fs-rms Jitter with SCR-based DCC | ||
- 레이아웃 사진 -
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