| IP명 | A 20-Gb/s 4-Tap Time-Domain DFE with Pulse Width Modulation for a DQ-DQS Matched Parallel Receiver | ||
|---|---|---|---|
| Category | Analog | Application | Memory |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1V |
| IP유형 | Hard IP | 동작속도 | 10GHz |
| 검증단계 | Silicon | 참여공정 | SS028-2502 |
| IP개요 | A 4-tap time-domain decision feedback equalizer (TD-DFE) is presented to implement a multi-tap DFE in a matched DQ-DQS tree architecture. Traditionally, matched architecture holds an advantage in terms of power noise immunity, but it suffers from low speed performance due to the unavailability of DFE application. By adopting the proposed TD-DFE, both high-speed operation and power noise immunity can be achieved within the matched architecture. |
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