| IP개요 |
This work presents a blocker-tolerant CMOS channel-selection low-noise amplifier (CH-SEL LNA) for front-end module (FEM)-less cellular transceivers. The proposed architecture combines feedforward N-path filtering, calibrated blocker cancellation, and output LC filtering to realize high-Q RF channel selectivity. By forming bandpass and band-rejection characteristics at multiple internal nodes, the circuit is designed to suppress TX leakage and out-of-band blockers before they degrade the following receiver stages. In addition, gain and phase calibration are employed to control the notch position, enabling tunable blocker rejection over the target frequency range. The proposed CH-SEL LNA is designed in a 28-nm CMOS process for mid-band 5G NR applications over 1.35-2.7 GHz. The design targets include a voltage gain of 18 dB, a minimum NF of 6 dB, a notch rejection ratio greater than 25 dB, and a current consumption of 20 mA from a 1 V supply. The active die area is 2.25 mm2. |
