| IP개요 |
In this proposal, we present an energy-efficient DSP for high-speed wireline ADC-based receivers under severe channel impairments. As data rates scale, conventional decision feedback equalizer (DFE) is limited by feedback dependency, making multi-tap implementation challenging. To address this, we adopt a history-block-based loop-breaking technique that converts recursive feedback into parallel forward computation. To reduce the overhead of redundant history blocks, the proposed DSP is designed to be reconfigurable, allowing the number of active blocks based on channel conditions. However, deep pipelining introduces significant register overhead, making sequential logic a dominant power contributor. To mitigate this, we employ custom low-power flip-flops to replace standard cell registers, significantly reducing power consumption. In addition, a low-power DSP data path employing localized dataflow, simplified arithmetic, and precomputation further reduces switching activity. The proposed architecture is implemented in 28 nm CMOS using a digital design flow and achieves improved energy efficiency and scalability for next-generation high-speed wireline systems. |
