| IP개요 |
we present an external capacitor-less low-dropout(LDO) regulator with a voltage spike detection circuit for the enhanced transient response and with the CMOS only sub-bandgap voltage reference(BGR) circuit operating in sub-threshold region. To enhance the transient response, transient enhancement scheme is adopted and stability concern is solved by using the cascade and current buffer compensation. The LDO operates with the reference voltage of 458mV from the sub-BGR and provides the output voltage of 1V. The simulated results show that the load regulation is 2.5mV/A and PSRR is -50dB at 1MHz. Total power consumption is 92μW and the chip area is 0.036mm2 with 0.18μm CMOS process. |
