| IP개요 |
The High-Luminosity Large Hadron Collider(HL-LHC) at CERN is anticipated to experience an radiation level up to 1 Grad of total ionizing dose (TID) over 10 years of operation. Nowadays, the large majority of the radiation-tolerant front-end ASICs in the detector systems of the LHC are built in a commercial 250nm CMOS technology, by adopting circuital and layout radiation-hardness techniques. In order to achieve radiation tolerance performances up to the expected level, characterization of the CMOS technology under the radiation must also be performed. It has been demonstrated that the radiation damage is smaller for devices with thiner gate oxide, but in ultra-scaled technologies various factors affects the radiation hardness of the circuit. These factors were analyzed for a limited list of 28nm CMOS processes and need to be evaluated for each process with which application is considered. |
