IP명 | Design of A Noise-robust Duobinary DFE Receiver | ||
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Category | Analog | Application | consumer electronics |
실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1V |
IP유형 | Hard IP | 동작속도 | 10Hz |
검증단계 | Silicon | 참여공정 | SS28-2001 |
IP개요 | A noise-robust duobinary DFE receiver is proposed as a method to implement single-ended memory interface. Since conventional duobinary signaling has three voltage levels, its voltage noise margin is severely degraded compared to that of binary signaling. Whereas, the proposed duobinary DFE receiver not only takes the both of advantages of duobinary signaling and integrating DFE also achieves the maximized voltage margin. | ||
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