| IP개요 |
This paper describes a new way of signaling and transceiver for high speed I/O interface. With proposed signaling, the transmitter eliminates the crosstalk noise induced by the channel by adjusting data timing. On the receiver side, a proposed decision-feedback equalizer (DFE) overcomes the limitations of conventional speculative DFEs to remove inter-symbol interference (ISI). The proposed hybrid signaling transceiver is fabricated in a 65-nm CMOS process and has a maximum data rate of 10Gb/s. It consumes 10mW per signaling without current digital-to-analog converter (IDAC) and clock driver from a 1.2 V supply. The proposed transceiver is designed using mixed type circuit |
