| IP개요 |
Modern long-reach high-speed serial links for data rate above 112 Gb/s are mostly based on the analog-digital converter (ADC) with extensive equalization in the DSP implemented in the fully digital circuit on the receiver (RX) side. This work intends to thoroughly compare the RX-side DSP equalizers in terms of silicon footprint, power consumption, and achievable speed for various orders of pulse-amplitude modulation (PAM). Despite the same target data rate (e.g., 224 Gb/s), PAM-4, PAM-6, and PAM-8 all have different required analog front-end (AFE) and DSP design specifications, and the optimized silicon performances of their DSPs will be a different one from another. In this work, the RX DSP equalizers will be implemented with a careful optimization strategy for each of PAM-4, PAM-6, and PAM-8, respectively, considering the relationships among multiple design parameters including the required DSP operation frequencies, bit precisions, and level of approximation. |
