| IP명 | A Low Power and Wide-Dynamic Range Cyclic Two-Step Time-to-Digital Converter in 180 nm CMOS | ||
|---|---|---|---|
| Category | Mixed | Application | 통신 |
| 실설계면적 | 3.8㎛ X 1.9㎛ | 공급 전압 | 3.3V |
| IP유형 | Hard IP | 동작속도 | 900MHz |
| 검증단계 | Silicon | 참여공정 | MS180-1602 |
| IP개요 | We describe a low power, small area time-to-digital converter (TDC) based on cyclic digital controlled oscillator (DCO) structure. The TDC is designed to be combined with an array of single photon avalanche diodes (SPAD) arranged in a digital silicon photomultiplier (SiPM) architecture to form an fluorescence life time sensor. The high dynamic range is achieved by using two individual counter two continuous conversion steps: coarse step and fine step. | ||
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