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IP Library

홈 | MPW / CDC | IP Library

"한국 반도체산업의 경쟁력"

IDEC에서 설계인력양성의 발판을 마련하겠습니다.

IP명 복수개의 부궤환 루프를 가진 초소형 크기의 위상고정루프
Category Analog Application 통신
실설계면적 3.8㎛ X 3.8㎛ 공급 전압 1.8V
IP유형 Soft IP 동작속도 1GHz
검증단계 Silicon 참여공정 MS180-1903
IP개요 To reduce the phase noise and jitter of the conventional PLL, the proposed PLL uses frequency voltage converter (FVC). When the output voltage (VCO input voltage) of the loop filter changes, the output voltage of the FVC changes in the opposite direction at a much higher sampling frequency in the negative feedback looped VCO. Thus, Whenever the VCO output frequency varies, the FVC works as a compensator and it results in VCO noise reduction. It has been simulated and proved by HSPICE in a CMOS 0.18μm 1.8V process
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