| IP명 | RNS-based FHE accelerator hardware | ||
|---|---|---|---|
| Category | Digital | Application | cryptography |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1.0V |
| IP유형 | Hard IP | 동작속도 | 333MHz |
| 검증단계 | Silicon | 참여공정 | SS28-2202 |
| IP개요 | This project proposes a hardware architecture that can accelerate polynomial operations on encrypted data using homomorphic encryption cryptography, based on lattice challenges (LWEs), a type of quantum-resistant cipher. In this process, we propose a method to solve the problem occurred by too long process, by introducing RNS to overcome the limitations of polynomial computation with very large modulus. Moreover suggest NTT butterfly modules to reduce time complexity to reduce convolution time of ultra-high-order polynomial. Since homomorphic encryption technology basically requires a lot of computation and data, it is not possible to fully implement a homomorphic accelerator at the ASIC level, but it is expected to be a good reference study for future research by implementing a simplified structure of the proposed hardware and be a good preknowledge for manufacturing ASIC. |
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