| IP명 | 빠른 안정화 속도를 가지는 인다이렉트 보상 LDO 설계 | ||
|---|---|---|---|
| Category | Analog | Application | LDO |
| 실설계면적 | 3.8㎛ X 3.8㎛ | 공급 전압 | 1.8V |
| IP유형 | Hard IP | 동작속도 | 20MHz |
| 검증단계 | Silicon | 참여공정 | MS180-1602 |
| IP개요 | A low-dropout voltage regulator(LDO) for SoC applications. The proposed LDO has fast transient response for a load step by using dynamic current-biasing and channel splitting compensation. For a 1.5~1.8V input voltage and 1.3V output voltage, the simulated undershoot and overshoot is only 8mV for load transient of 10uA to 10mA within edge times of 100 ns. The proposed LDO dissipates 70uA at no-load condition. The circuit was designed by a 0.18㎛ CMOS technology. | ||
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