| IP개요 |
This paper presents a 200-Mb/s to 3-Gb/s half-rate referenceless clock and data recovery (CDR) circuit in 180nm CMOS process with 1.8V supply voltage. A bidirectional frequency detector (FD) is proposed to eliminate the harmonic locking issue and reduce the frequency acquisition time. A frequency band selector for wide-range the voltage-control oscillator (VCO) is also presented to select an exact frequency band of the VCO. The simulation shows the CDR achieves 10-ps peak-to-peak jitter at 3Gb/s and the frequency acquisition time of 12.9 ?s. This CDR is type of mix-circuit. |
