| IP개요 |
This paper presents a 500KS/s 12-bit SAR ADC with a charge recycling scheme. To overcome the problem that SAR ADCs (Successive Approximation Register Analog-to-Digital Converter) have a large CDAC (Capacitor Digital-to-Analog Converter), the proposed architecture uses MSB-split capacitors. Therefore total capacitance is half of the conventional ones. With the charge recycling, ADC reduces switching power consumption. This architecture is based on Mixed signal circuit of 0.18μm CMOS Process and supply voltage is 1.8 V. The external clock frequency is 6.25 MHz of this synchronous architecture. It can be compared with previous SAR ADC circuit which is conventional type of SAR ADC. |
