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IP명 128-bit AES Block Cipher Core for Three Operation Mode
Category Digital Application processor
실설계면적 3.8㎛ X 3.8㎛ 공급 전압 3.3V
IP유형 Hard IP 동작속도 50000000Hz
검증단계 FPGA 참여공정 MS180-1602
IP개요 The advanced encryption standard (AES), most widely used to encrypt or decrypt data, is computationally intensive applications. In order to implement the AES encryption algorithm, the data must go through complicated operations composed of several steps. The AES encryption algorithm is generally used for internet-based applications. We propose the selection of the operation mode for the block cipher, the realization of the AES core. The implementation results obtained using the AES block cipher processors.
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