IP명 | A New 5.8GHz Transconductor-type Quadrature Generator for the DSRC Application | ||
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Category | Analog | Application | RFIC |
실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 2.2V |
IP유형 | Hard IP | 동작속도 | 2.1GHz |
검증단계 | Silicon | 참여공정 | SS65-1603 |
IP개요 | A RF front-end of the 5.8 GHz integrated CMOS dedicated short range communication (DSRC) receiver for the Korea/Japan electronic toll collection system is presented. The receiver uses low-IF conversion architecture for high sensitivity and low-power consumption. To solve image problem in the low-IF receiver, 10 MHz IF and 40 MHz IF are chosen for Korean and Japanese DSRC standards, respectively, since they make no image signals exist in image band. A singlequadrature mixer with the proposed transconductor-type quadrature generator in RF signal path is also adopted which has accurate quadrature characteristic in 5.8 GHz frequency. When the RF front-end of the integrated 5.8 GHz DSRC receiver is implemented using 0.65 nm CMOS technology, the receiver achieves the overall noise figure of less than 5 dB with image rejection ratio of more than 30 dB. The RF front-end of the 5.8 GHz DSRC receiver dissipates 45 mA with 1.2 V supply voltage. |
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