| IP개요 |
In the proposed hardware, we have shown through simulation that the performance of the new digital SNN algorithm utilizing the TCAMs can outperform state of the art PIMs. In particular the learning performance is highly efficient as well robust as compared to analog MAC computation approaches taken by conventional PIMs. In this research project, we wish to take a leap toward actual usability and develop our architecture to perform unsupervised learning using a non-volatile PIM architecture. Furthermore, we also want to develop a controller based on a simple RISC-V (RV32I) ISA which will act as a microcontroller that can automatically start a program upon startup. This will enable us to have more flexibility in dealing with autonomous control for individual chips. In addition, this microcontroller based approach will allow several chips to perform independent tasks to process a larger network. Another front that we want to explore is creating a comprehensive test structure to fully understand and access the TCAM based on MRAM cell. We are currently developing a version without the non-volatile cells using the 28nm process and our proposed project will the conversion of that architecture to non-volatile PIM and a RISC-V microcontroller as well as a test structure for optimal access of the MRAM cells. |
