| IP개요 |
This IP presents an energy-efficient wordline driver for a triple level cell 3D NAND flash. Unlike conventional circuit that has a large charge pump and high-voltage regulators operating under the inefficient stepped-up voltage, the proposed circuit has a distributed charge pump (CP) that directly drive the wordlines, aided by a charge compensating regulator that operate under the nominal supply and produces a ripple free output. The proposed voltage driver for a 39 wordline layer is fabricated in 180nm UHV process and it consumes 99.8nJ from a 2.2V during 1 unit of program pulse and verify period, which is more than 2.1x improvement in energy efficiency compared to the conventional scheme. |
