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홈 | MPW / CDC | IP Library

"한국 반도체산업의 경쟁력"

IDEC에서 설계인력양성의 발판을 마련하겠습니다.

IP명 An Energy-Efficient Voltage Step-up System for 3D NAND Flash using Charge-Compensating Regulator
Category Analog Application memory
실설계면적 3㎛ X 3㎛ 공급 전압 2.2V
IP유형 Hard IP 동작속도 40MHz
검증단계 Silicon 참여공정 HM-2002
IP개요 This IP presents an energy-efficient wordline driver for a triple level cell 3D NAND flash. Unlike conventional circuit that has a large charge pump and high-voltage regulators operating under the inefficient stepped-up voltage, the proposed circuit has a distributed charge pump (CP) that directly drive the wordlines, aided by a charge compensating regulator that operate under the nominal supply and produces a ripple free output. The proposed voltage driver for a 39 wordline layer is fabricated in 180nm UHV process and it consumes 99.8nJ from a 2.2V during 1 unit of program pulse and verify period, which is more than 2.1x improvement in energy efficiency compared to the conventional scheme.
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