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홈 | MPW / CDC | IP Library

"한국 반도체산업의 경쟁력"

IDEC에서 설계인력양성의 발판을 마련하겠습니다.

IP명 An ultra low-power ECoG signal recording analog front-end IC
Category Analog Application neural recording
실설계면적 0.402㎛ X 0.208㎛ 공급 전압 1V
IP유형 Hard IP 동작속도 100kHz
검증단계 Silicon 참여공정 HM-1907
IP개요 an implantable analog front-end integrated circuit for ECoG recording incorporating LNA and SAR ADC is presented. The LNA designed based on inverter stacking technique achieves excellent NEF performance by using proposed floating body technique. By using the gain boosting topology, CMFB compensation technique, and T-resistor network in capacitive feedback, more accurate frequency response is achieved and enables high-fidelity ECoG recording. The LNA operating at 1-V supply achieves 1.27 of NEF with 40 dB of voltage gain, 520 Hz bandwidth, 6.04 μVrms of integrated input referred noise and 15.5 nW power consumption. The designed SAR ADC uses a VCM-based monotonic capacitor switching scheme saving 97.66 % of switching power with quarter of CDAC area compared to conventional SAR ADC. Proposed EVEN/ODD technique using new dynamic logic block architecture reduces the number of digital logic blocks, digital power consumption, and logic delay. Asynchronous clock and non-binary weight redundant capacitor techniques are used to improve the ADC power efficiency and linearity. The ECoG recording AFE IC designed using TSMC 1P9M 65-nm CMOS process occupies 0.083 mm² of chip area.
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