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IP Library

홈 | MPW / CDC | IP Library

"한국 반도체산업의 경쟁력"

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IP명 A Low Power SoC for Digital Signal Processing in Embedded System
Category Digital Application Signal Processing
실설계면적 2㎛ X 2㎛ 공급 전압 3.3V
IP유형 Hard IP 동작속도 50MHz
검증단계 FPGA 참여공정 MS180-1902
IP개요 In this paper, we propose a low power SoC for digital signal processing (DSP) in embedded system. In order to enhance a performance of a main processor with minimized design area, we designed the digital filter accelerator. And, we apply the structure of 4-order IIR filter based on fixed-point computation. By supporting the communication protocol that is mainly used in the embedded system, the system is available to be applied to various of applications. We verify the digital filter accelerator by comparing result of simulation. Magnachip/Hynix 180nm CMOS technology. Our design is operated in 3.3V, 50 MHz. Our circuit type is Digital.
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