| IP명 | A CMOS Image Sensor-based Stereo Matching Accelerator with Focal-plane Sparse Rectification and Analog Census Transform | ||
|---|---|---|---|
| Category | Digital | Application | Vision User Interface |
| 실설계면적 | 3.984㎛ X 3.984㎛ | 공급 전압 | 1.2V |
| IP유형 | 동작속도 | 200Hz | |
| 검증단계 | Silicon | 참여공정 | SS65-1703 |
| IP개요 | A low-latency and low-power stereo matching accelerator is monolithically integrated with a CMOS image sensor (CIS) for mobile applications. To reduce the overall latency, focalplane processing is adopted by using the proposed analog census transform circuit (ACTC), and the image readout is pipelined with the following stereo matching process. In addition, a novel focalplane rectification pixel array (FRPA) merges the rectification with the image readout without any additional processing latency. For area-efficient pixel design, sparse rectification is proposed, and the image rectification is implemented with only two additional switches in each pixel. A stereo matching digital processor (SMDP) is integrated with the CIS for cost aggregation. We present the full design including the layout with a 65 nm CMOS process, and the FRPA, the ACTC, and the SMDP achieve 11.0 ms latency with complete stereo matching stages, which is suitable for a smooth user interface. As a result, the 2-chip stereo matching system dissipates 573.9 m J/frame and achieves 17% energy reduction compared to a previous stereo matching SoC. |
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- 레이아웃 사진 -
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