| IP명 | Efficient Successive-Cancellation Polar Decoder Based on Redundant LLR Representation | ||
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| Category | Digital | Application | Communication |
| 실설계면적 | 3㎛ X 3㎛ | 공급 전압 | 3.3V |
| IP유형 | Soft IP | 동작속도 | 300Hz |
| 검증단계 | Silicon | 참여공정 | MS180-1704 |
| IP개요 | Efficient Successive-Cancellation Polar Decoder Based on Redundant LLR Representation - Test vector, interface, decoding core - Tree based architecture - 4-bit decoding - vector overlapping (overlapping factor = 2) - gate count : 4300000 |
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