| IP명 |
Design of Stacked FET Power Amplifier for high frequency in 65nm CMOS process |
| Category |
Analog |
Application |
Power Amplifier for High Frequency |
| 실설계면적 |
4㎛ X 4㎛ |
공급 전압 |
1.2~1.5V |
| IP유형 |
Hard IP |
동작속도 |
60GHz |
| 검증단계 |
Silicon |
참여공정 |
SS65-1702 |
| IP개요 |
New design of Power amplifier is proposed with all revised electrode structure transistor for lower resistance of gate and lower capacitances of Cds for high Gain at Millimeter-wave frequency with simulation. Simulated gain of 5stacked FET PA is 23dB at 57GHz and 3dB Bandwidth is 9.4GHz with 1μm x48 all revised type FET. The driving voltage of FET is 1.5V for maximum swing and gate voltage is 1V in 65nm normal CMOS process. |
- 레이아웃 사진 -
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