| IP명 | 12-bit 100kS/S SAR ADC | ||
|---|---|---|---|
| Category | Mixed | Application | Sensor applications |
| 실설계면적 | 5㎛ X 4㎛ | 공급 전압 | 3.3V |
| IP유형 | Hard IP | 동작속도 | 100000Hz |
| 검증단계 | Simulation | 참여공정 | MS350-1701 |
| IP개요 | In recent years, the Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) has been actively investigated owing to its power efficiency. Specifically, the SAR ADC does not dissipate static power at all if a preamplifier is not used. In spite of the power efficiency of the SAR ADC, the requirement of a large number of clock cycles for a single conversion is a major weakness for high-speed operation. The drawbacks of the SAR ADC are currently being overcome with advancements in the CMOS process technology and several speed enhancement techniques. It is difficult to guarantee linearity of the high-resolution data converters (≥ 12-bits) because of component mismatches. In order to design high-resolution data converters, the size of unit component should be large enough to guarantee a linearity of the ADC. However, a larger capacitance consumes more power and requires much longer settling time. In this design, segmented DAC architecture in which the 3 MSBs are thermometer-encoded and the remaining 9 LSBs are binary encoded was implemented to alleviate strict matching requirement and reduce switching power consumption. Because the MIM capacitor is the stacked capacitor, linearity of capacitive DAC can be degraded by parasitic-induced capacitance. Furthermore, it is extremely difficult to implement a common centroid layout in a large 2-dimensional capacitor array, resulting in huge non-linearity caused by systematic and random mismatch errors. In order to overcome these problems, custom-designed MOM (Metal-Oxide-Metal) finger capacitor was designed using parasitic extraction. Owing to its parallel structure, the linearity of capacitive DAC made up of metal finger capacitor is insensitive to parasitic-induced capacitance. Additionally, random and systematic mismatch errors can be suppressed by simple common centroid layout due to the 1-dimensional capacitor array layout. Based on previous our work, the size of unit capacitor was chosen as 5fF to satisfy a DNL<0.5LSB. To minimize the occupied area, metal layers 1, 2, 3, and 4 are stacked together with minimum metal spacing. Prior to fabrication, post-layout simulation was performed to predict performances of the fabricated chip using cadence parasitic extraction (PEX) and SPECTRE. Fig 1 shows layout of the designed ADC. It operates with 1.8V supply up to 100kS/s and occupies 0.48mm2. Fig 2 is a FFT simulation result. The SNDR and SFDR obtained from FFT simulation were 71.2dB and 80.6dB, respectively. The corresponding ENOB is 11.5bit. The figure of merit calculated from simulation results is 93.22fJ/conversion-step. |
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