| IP개요 |
In this proposal, a low power 14-b analog to digital converter(ADC) is proposed in a 0.18um CMOS technology. The proposed low power ADC comprises a 2nd-order feedforward structure and the 2nd-order modulator which is consist of an inverter based integrators for the area and power efficiency. A simple counter is implemented as a decimation filter instead of a complex formed decimation filter. The simulated results show that the proposed ADC achieved the SNDR of 80.44 dB, the SFDR of 86.12dB, and the ENOB (effective number of bits) of 13.07 bits. The power consumption including all the digital circuits is 4.311uW at the sampling frequency of 25Hz under 1.8V supply voltage and the core area is 850um x 650um. The FoM (figure of merit) is 151.12dB derived from Schreier's FoM calculation. |
