| IP개요 |
A 1.2-V 50-MS/s 12-bit pipelined SAR ADC with an input range calibration scheme for a fine ADC is proposed. The proposed input range calibration for the fine ADC improves the linearity of the pipelined SAR ADC and results in increasing the dynamic and static performance. The proposed pipelined SAR ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1.2-V supply voltage. The simulated DNL is improved from 1.52 LSB to 0.25 LSB using the proposed input range calibration scheme. The SNDR is simulated to be 71.46 dB. The chip area of the pipelined SAR ADC is 500 × 480 μm2 |
