| IP명 | A 5Gb/s Half-Rate Forwarded-Clock Receiver Correcting Input Duty-Cycle Distorted Data in 65nm CMOS | ||
|---|---|---|---|
| Category | Analog | Application | wireline receiver |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1V |
| IP유형 | Hard IP | 동작속도 | 2.5GHz |
| 검증단계 | Silicon | 참여공정 | SS65-1603 |
| IP개요 | A 5Gb/s Half-Rate Forwarded-Clock Receiver Correcting Input Duty-Cycle Distorted Data | ||
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