| IP명 | Voltage regulator의 전력노이즈와 I/O 회로 지터에 대한 영향 분석 회로 | ||
|---|---|---|---|
| Category | Mixed | Application | 연구 |
| 실설계면적 | 5㎛ X 4㎛ | 공급 전압 | 3.3V |
| IP유형 | Hard IP | 동작속도 | 1GHz |
| 검증단계 | Silicon | 참여공정 | MS350-1602 |
| IP개요 | electromagnetic compatibility (interference and susceptibility) of integrated circuit is analytically modeled to predict immunity issues in early design phase of the IC and to improve protection on package/board. In this design, there are two circuits to be tested for the electromagnetic susceptibility; an on-chip voltage regulator module (VRM) a modified version of the ubiquitous 8051 microcontroller,which are the most noisy component of emerging three dimensional ICs (3D ICs) and the representative circuit of digital system, respectively. On-chip VRM with supply power of 3.3 V and maximum operating frequency of 400 MHz is designed based on 350nm Magna/Hynix process together with high-speed output buffers with maximum data rate of 1.6 Gbps. The 8051 is based on the open-source synthesizable VHDL model which is 100% instruction compatible with the commercially-available 8051. Analytical model has been developed for both analog and digital circuits to predict the performance degradation due to electromagnetic events. |
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- 레이아웃 사진 -
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