| IP명 | Energy-Efficient Deep Learning Accelerator Hardware | ||
|---|---|---|---|
| Category | Digital | Application | Mobile System |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1.2V |
| IP유형 | Hard IP | 동작속도 | 1000000Hz |
| 검증단계 | Silicon | 참여공정 | SS65-1603 |
| IP개요 | The design is expected to have significantly enhanced energy efficiency, while still meeting tight performance requirements to deal with up-to-date deep learning algorithms. We propose to take multiple-level approach to maximize system efficiency, and specialized digital design flow will be adopted to realize a robust physical design. | ||
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- 레이아웃 사진 -
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