| IP개요 |
A 10Gb/s DLL-based reference-less CDR for clock-embedded signaling in 65nm CMOS is presented. The proposed receiver operates in mixed mode and the supply voltage is 1.0 V. To save the channel for forwarded clock and eliminate the external reference, clock-embedded signaling scheme is used in this proposal. DLL-based architecture is adopted to save the power consumption. To accomplish a 10Gb/s data rate, inter-symbol-interference (ISI) jitter reduction technique is presented. ISI jitter reduction reduces the bit-error rate (BER) of the receiver by enlarging the sampling margin. To save the power consumption, new deskew method which is done by sub-DLL is presented to use D-flip flops instead of sense-amps. The sub-DLL also gives tolerance to PVT variations to the receiver. The cadence simulation results, which were done with the 65nm process model, verify the operation of the proposed schemes |
