| IP개요 |
A 0.8 ? 1.5 GHz All-Digital Phase Locked Loop (ADPLL) using 1-step Vernier Time-to-Digital Converter (TDC) for using MIPI M-PHY system. The proposed TDC uses a 1-step structure with an inverter chain delay structure which has several advantages such as wide time conversion range and simple structure in the form of the first regular delay. By using advantages of two delay structures, the proposed TDC can have wide time conversion range, small size, low power consumption, and high time resolution. |
