| IP명 | Design of Millimeter-wave Power Amplifier using stacked-FET | ||
|---|---|---|---|
| Category | Analog | Application | RF CMOS circuit |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 1.2V |
| IP유형 | Hard IP | 동작속도 | 60GHz |
| 검증단계 | Silicon | 참여공정 | SS65-1603 |
| IP개요 | New methodology for Millimeter-wave Power Amplifier (PA) is proposed for high output power by adjusting for in-phase voltage stacking at each stacked FET. Output Gain is higher than normal architecture about 4 dBm. The circuits are simulated by 65 nm CMOS process and driving voltages and gate voltages of FETs are adjusted for maximum output power. The maximum gain of 5-stacked FET PA is 17.9 dB at 60.4 GHz and bandwidth (BW) is 10 GHz | ||
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