| IP명 | LZ4 Compression Hardware Accelerator | ||
|---|---|---|---|
| Category | Digital | Application | processor |
| 실설계면적 | 4㎛ X 4㎛ | 공급 전압 | 3.3V |
| IP유형 | Hard IP | 동작속도 | 100000000Hz |
| 검증단계 | FPGA | 참여공정 | SS65-1601 |
| IP개요 | Our key idea is to suppress the overhead of transaction logging through the high throughput hardware compression. Compared to software compression, our hardware accelerator scored 6x better performance in compression throughput. We will fabricate using Samsung 65 nm CMOS technology. Our design is operated in 3.3V, 100 MHz. Our circuit type is Digital. | ||
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